Field of the Invention
The present invention relates to a solid-state imaging apparatus and an imaging device. Priority is claimed on Japanese Patent Application No. 2014-106347, filed May 22, 2014, the content of which is incorporated herein by reference.
Description of Related Art
As an example of a solid-state imaging apparatus using a time to digital converter single slope (tdcSS) type AD conversion circuit obtained by combining a time to digital converter (TDC) type AD conversion circuit with a single slope (SS) type AD conversion circuit, a configuration disclosed in the publication of Japanese Unexamined Patent Application, First Publication No. 2011-55196 is known. FIG. 13 shows part of the configuration of the tdcSS type AD conversion circuit in accordance with a first conventional example. Hereinafter, the configuration and the operation of the circuit shown in FIG. 13 will be described.
The circuit shown in FIG. 13 has a comparison section 1031, a latch section 1033, a count section 1034, and a buffer circuit BUF. The comparison section 1031 has a voltage comparator COMP configured to receive inputs of an analog signal Signal serving as an AD conversion target and a reference signal Ramp which decreases with the passage of time and output a comparison signal CO based on a result of comparing the analog signal Signal with the reference signal Ramp. The latch section 1033 has latch circuits L_0 to L_7 configured to latch logic states of a plurality of phase signals CK[0] to CK[7] having different phases from each other. The count section 1034 has a counter circuit CNT configured to perform a count operation based on the phase signal CK[7] output from the latch circuit L_7. A control signal RST is a signal used for performing a reset operation of the counter circuit CNT.
In the comparison section 1031, a time interval (a magnitude of a time axis direction) based on an amplitude of the analog signal Signal is generated. The buffer circuit BUF is an inverting buffer circuit configured to invert an input signal and output the inverted input signal.
The latch circuits L_0 to L_7 constituting the latch section 1033 are in an enable (valid or active) state and output the input phase signals CK[0] to CK[7] without change when a control signal Hold from the buffer circuit BUF is in a High (H) state. In addition, the latch circuits L_0 to L_7 are in a disable (invalid or hold) state when the control signal Hold from the buffer circuit BUF is transitioned from the H state to the Low (L) state and latch logic states of the input phase signals CK[0] to CK[7].
Next, an operation of the circuit according to the first conventional example will be described. FIG. 14 shows waveforms of the reference signal Ramp, the analog signal Signal, a start pulse StartP, the phase signals CK[0] to CK[7], the comparison signal CO, the control signal Hold from the buffer circuit BUF, and output signals Q0 to Q7 of the latch circuits L_0 to L_7 of the latch section 1033. The horizontal direction of FIG. 14 represents time and the vertical direction of FIG. 14 represents a voltage.
First, the generation of the phase signals CK[0] to CK[7] starts at the first timing related to the comparison start in the comparison section 1031 and the generated phase signals CK[0] to CK[7] are input to the latch circuits L_0 to L_7 of the latch section 1033. Because the control signal Hold from the buffer circuit BUF is in the H state, the latch circuits L_0 to L_7 are in the enable state and the phase signals CK[0] to CK[7] are output without change.
The count section 1034 performs a count operation based on the phase signal CK[7] output from the latch circuit L_7 of the latch section 1033. In this count operation, a count value increases or decreases at a rising or falling timing of the phase signal CK[7]. The comparison signal CO from the comparison section 1031 is inverted at a second timing at which a voltage of the analog signal Signal substantially coincides with that of the reference signal Ramp. After the comparison signal CO is buffered by the buffer circuit BUF, the control signal Hold from the buffer circuit BUF is in the L state at the third timing.
Thereby, the latch circuits L_0 to L_7 are in the disable state. At this time, the logic states of the phase signal CK[0] to CK[7] are latched in the latch circuits L_0 to L_7. When the latch circuit L_7 stops the operation, the count section 1034 latches the count value. Digital data corresponding to the analog signal Signal is obtained by the logic state latched by the latch section 1033 and the count value latched by the count section 1034.
Further, a configuration disclosed in the publication of Japanese Unexamined Patent Application, First Publication No. 2012-39386 has been proposed. FIG. 15 shows part of the configuration of a tdcSS type AD conversion circuit according to a second conventional example. Hereinafter, a configuration and an operation of the circuit shown in FIG. 15 will be described.
The circuit shown in FIG. 15 has a comparison section 1031, a latch control section 1032, a latch section 1033, and a count section 1034. The comparison section 1031 and the count section 1034 are the same as the comparison section 1031 and the count section 1034 shown in FIG. 13.
The latch control section 1032 has an inverting delay circuit DLY and an AND circuit AND1 and generates a control signal for controlling the operation of the latch section 1033. A comparison signal CO is input from the comparison section 1031 to the inverting delay circuit DLY. The inverting delay circuit DLY inverts the comparison signal CO and outputs a delayed comparison signal xCO_D. The inverted comparison signal xCO_D from the inverting delay circuit DLY and the comparison signal CO from the comparison section 1031 are input to the AND circuit AND1. The AND circuit AND1 outputs a control signal Hold_L obtained by taking a logical product (AND) of the comparison signal xCO_D and the comparison signal CO.
The latch section 1033 has latch circuits L_0 to L_7 and an AND circuit AND2. The latch circuits L_0 to L_7 are the same as the circuits L_0 to L_7 shown in FIG. 13. The AND circuit AND2 outputs a control signal Hold_C obtained by taking a logical product (AND) of the comparison signal xCO_D from the inverting delay circuit DLY of the latch control section 1032 and a control signal Enable to the latch circuit L_7.
Next, an operation of the circuit according to the second conventional example will be described. FIG. 16 shows waveforms of the start pulse StartP, the phase signals CK[0] to CK[7], the phase signals CK[0] to CK[7], the comparison signal xCO_D, the comparison signal CO, the control signal Hold_L from the AND circuit AND1, the control signal Enable, the control signal Hold_C from the AND circuit AND2, and the output signals Q0 to Q7 of the latch circuits L_0 to L_7 of the latch section 1033. The horizontal direction of FIG. 16 represents time and the vertical direction of FIG. 16 represents voltage.
Hereinafter, different parts from the operation of the circuit according to the first conventional example will be described. After a first timing related to a comparison start in the comparison section 1031, the comparison signal CO from the comparison section 1031 is in the L state until voltages of the analog signal Signal and the reference signal Ramp input to the comparison section 1031 substantially coincide. While the comparison signal CO is in the L state, the comparison signal xCO_D from the inverting delay circuit DLY is in the H state. Because the comparison signal xCO_D from the inverting delay circuit DLY is in the H state and the comparison signal CO from the comparison section 1031 is in the L state, the control signal Hold_L from the AND circuit AND1 is in the L state. Thus, the latch circuits L_0 to L_6 are in the disable state.
On the other hand, because the control signal Enable is in the H state at the first timing related to the comparison start in the comparison section 1031 and the comparison signal xCO_D from the inverting delay circuit DLY is in the H state, the control signal Hold_C from the AND circuit AND2 is in the H state. Thus, the latch circuit L_7 is in the enable state.
Subsequently, the comparison signal CO from the comparison section 1031 is inverted at the second timing at which the voltages of the analog signal Signal and the reference signal Ramp substantially coincide. Because the comparison signal xCO_D from the inverting delay circuit DLY is in the H state and the comparison signal CO from the comparison section 1031 changes from the L state to the H state, the control signal Hold_L from the AND circuit AND1 changes from the L state to the H state. Thereby, the latch circuits L_0 to L_6 are in the enable state.
Further, the comparison signal xCO_D from the inverting delay circuit DLY changes from the H state to the L state at the third timing at which a predetermined time has elapsed from the timing at which the comparison signal CO from the comparison section 1031 has been inverted. Thereby, because the control signal Hold_L of the AND circuit AND1 and the control signal Hold_C of the AND circuit AND2 change from the H state to the L state, the latch circuits L_0 to L_7 are in the disable state.
In the above-described operation, it is possible to reduce current consumption as compared with the first conventional example because the latch circuits L_0 to L_6 operate only in the period from the second timing to the third timing.
As a specific configuration of the inverting delay circuit DLY, for example, the application of a so-called delay line in which inverter circuits are connected in multiple stages disclosed in ITE Technical Report Vol. 37, No. 29 is considered.
However, the degradation of AD conversion precision is caused by power supply noise and ground bounce in a conventional tdcSS type AD conversion circuit and a solid-state imaging apparatus using the same.
In a column circuit provided in the solid-state imaging apparatus using the conventional tdcSS type AD conversion circuit, a comparison section 1031, a latch control section 1032, a latch section 1033, and a count section 1034 are disposed for every column in correspondence with each column of an array of pixels disposed in a matrix. Although a power supply voltage VDD is supplied to each section of the column circuit, wiring resistance further increases when the column circuit is closer to a center column than an end column (that is, the column circuit is farther from the power supply) and therefore a larger voltage drop occurs and the power supply voltage VDD decreases. In addition, when current consumption in the circuit further increases, the voltage drop becomes larger. In addition, for a similar reason, the ground voltage GND is further raised when the column circuit is closer to the center column than the end column (that is, the column circuit is farther from the ground). For example, even when the power supply voltage VDD=1.5 [V] and the ground voltage GND=0 [V] in the example of the end column of the column circuit, the power supply voltage VDD=about 1.2 [V] and the ground voltage GND=about 0.3 [V] in the center column of the column circuit in some cases.
Comparison signals CO from the comparison sections 1031 of all columns are inverted substantially simultaneously during an AD conversion period (for example, an AD conversion period of a reset level substantially constant in all pixels) and therefore the inverting delay circuit DLY and the latch circuits L_0 to L_6 may start (may be in the enable state) substantially simultaneously. In this case, transient currents flow substantially simultaneously within the inverting delay circuits DLY and the latch circuits L_0 to L_6 of all the columns and therefore transient bounces of the power supply and the ground by these transient currents and wiring resistance (the transient voltage leakage around the power supply voltage VDD=1.2 [V] and the ground voltage GND=0.3 [V]) occur particularly in the vicinity of the center column of the column circuit.
In particular, because a through-current flowing through a transistor constituting an inverter circuit is large when a logic state of an input signal has been inverted in the inverter circuit, the bounces of the power supply and the ground tend to occur. In addition, a propagation delay time of the inverter circuit significantly depends upon a difference between the power supply voltage and the ground voltage.
In the conventional tdcSS type AD conversion circuit, the latch circuits L_0 to L_7 are in the disable state at the third timing at which a delay time has elapsed in the inverting delay circuit DLY from the second timing at which operations of the latch circuits L_0 to L_6 have started substantially simultaneously and the logic states of the phase signals CK[0] to CK[7] are latched. However, in the vicinity of the center column of the column circuit, the delay time of the inverting delay circuit DLY changes and the third timing, which is the latch timing, changes depending on the voltages (bounce magnitudes) of the power supply and the ground.
In particular, in the inverting delay circuit DLY based on a configuration in which a plurality of inverter circuits are connected, a delay time tDLY of each inverter circuit changes depending on a change in the voltages (bounce magnitudes) of the power supply and the ground and the delay time tDLY of each inverter circuit is accumulated. Thereby, there is a possibility of the delay time of the inverting delay circuit DLY greatly changing and it being difficult for the latch circuits L_0 to L_7 to accurately latch logic states of the phase signals CK[0] to CK[7]. This problem is likely to occur when comparison signals CO from a large number of comparison sections 1031 change substantially simultaneously. As a result, AD conversion precision is likely to be degraded.